• Ownership: Every team member has a significant impact on our success. With great responsibility comes fair rewards, allowing you to directly benefit from the value you bring to the team.
• Challenge: We encourage you to build solutions as you see fit and question the status quo. If you thrive in an environment where you can innovate and challenge conventional wisdom, this is the place for you.
• Startup Atmosphere, Enterprise Resources: We combine the agility and innovation of a startup with the resources and support of an established enterprise, providing you with the best of both worlds.
• Cutting-edge technology: Ultra low-latency infrastructure, FPGA, latest C++ standards and innovations.
• No-Bullshit Approach: We value honesty, transparency, and efficiency above all else.
• Freedom and Responsibility: We trust our team members to make the right decisions and give them the freedom to do so. This comes with the expectation that everyone takes responsibility for their actions and contributes to our overall success.
• ‍Fair Compensation: base salary from 120K USD gross + uncapped PnL bonuses. We also provide lots of other benefits like in-house wellness coach, health insurance, gym compensation, lunch delivery, relocation support if needed.

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• Strong knowledge of the FPGA microarchitecture
• Experience working with 10GBASER standard
• Experience in SystemVerilog development for at least 3 years
• Ability to write comprehensive Testbench with the FAIL/PASS automation
• TCL, Makefile, Python

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• HFT experience